ConnectX-7 and ConnectX-8: specify the whole connection.

Start with the adapter, not “an 800G optic.”

ConnectX identifies a controller family, not one universal front-panel interface. Record the complete adapter ordering part number (OPN), server model, port location, firmware and intended protocol. A PCIe card, an OCP adapter and an integrated GPU-tray implementation can present different cages and port groupings.

NVIDIA’s ConnectX-8 manual makes this distinction concrete: C8180 OSFP configurations include a single 800Gb/s XDR InfiniBand port and a two-port 400GbE Ethernet arrangement; C8240 uses two QSFP interfaces with up to 400Gb/s per port. Those are model-specific configurations, not interchangeable descriptions of one optical link. ConnectX-8 manual ↗

Keep three rates separate: PCIe transfer capability, host-to-module electrical signaling and the optical interface. The rate printed on the NIC does not describe all three.

OSFP IHS versus RHS: where does the heat go?

NVIDIA’s LinkX documentation describes RHS for its OSFP ConnectX-7 adapters; the ConnectX-8 manual also specifies RHS-only OSFP cages. Its 100G-PAM4 LinkX portfolio pairs IHS twin-port modules with specified air-cooled switches and RHS modules with specified adapter or system cages. This is a mechanical and thermal requirement, not merely a cosmetic lid choice. CX7 interfaces · CX8 manual · LinkX shell definitions

Do not turn that into “all switches use IHS” or “liquid cooling means any flat top fits.” Read the actual switch or server integration. Verify the module’s power class and cooling requirement even when the shell clears the cage.

Single-port, twin-port and 800G are different attributes.

The first two rows describe the cited 100G-PAM4 portfolio. The third is NVIDIA’s specific MMS4A20 XDR example, specified for up to 500 m. It does not turn every 800G OSFP into a compatible part. 100G-PAM4 portfolio · MMS4A20 specification

An 800G package containing two 400G engines cannot be treated as a single 800G DR4 optical endpoint. Even if the connector shell matches, lane signaling, optical organization and logical port allocation may not. Host electrical lanes and optical lanes also need separate entries when a module performs conversion between them.

Worked connection: one switch module, two NICs.

Consider a documented twin-port 2×400G parallel-optics switch module serving two separate 400G adapters. Each optical port runs to a matching single-port module at a NIC. With two straight MPO assemblies, the connection record contains:

• 2 logical links, each carrying 400Gb/s.
• 3 physical transceiver modules: one twin-port switch module and two NIC modules.
• 2 fiber assemblies, each with its own endpoint map, polarity and loss record.

This count excludes leaf-to-spine links, spare parts and intermediate patching. The twin-port housing is not two modules, and a two-port optical presentation does not automatically require one fanout harness. Confirm the precise optical application before choosing straight fibers or a breakout. NVIDIA transceiver and fiber arrangements ↗

For the cited NVIDIA 100G-PAM4 SR4/DR4 designs, check MPO-12/APC explicitly; do not substitute a familiar UPC multimode assembly. Separately record pinned versus unpinned mating requirements and the populated fiber positions.

What belongs in the final connection record?

1. Both hosts: exact platform, adapter OPN, port, firmware and configured protocol.
2. Both modules: package, IHS/RHS construction, power requirement, electrical application and optical application.
3. Every lane group: one port or multiple ports, per-port rate and supported splitting configuration.
4. The complete fiber: media, length, polish, pinning, connector positions, polarity and intermediate losses.
5. Acceptance: recognition, stable link, FEC/error counters, temperature and workload behavior under the intended operating conditions.

Use the exact firmware matrix to resolve qualification. A readable EEPROM or a successfully inserted module establishes neither end-to-end compatibility nor thermal margin.

Sources and applicability

Original WBN engineering guidance, checked against the sources below on 2 November 2026. Named NVIDIA parts illustrate documented interfaces; they do not establish WBN product availability or qualification. Use the exact adapter OPN, platform integration and firmware support matrix for procurement.

1. NVIDIA LinkX — ConnectX and DGX interface overview

   OSFP/QSFP adapter variants and cage-mounted riding heat sinks; online guide checked 2 November 2026.

2. NVIDIA ConnectX-8 SuperNIC User Manual

   28 May 2026 edition. Port configurations and specifications, including C8180/C8240 and the RHS-only OSFP requirement.

3. NVIDIA LinkX 100G-PAM4 Product Line Overview

   Shell, port and lane terminology for this specific 100G-PAM4 product line.

4. NVIDIA MMS4A20 800Gbps DR4 RHS transceiver

   XDR example: four 200G electrical/optical lanes, MPO-12/APC, single mode and stated 500 m maximum.

5. NVIDIA Transceivers and Fiber Details: 100G-PAM4

   Twin-port to single-port connections and model-specific optical connector requirements.

Continue the engineering record

• Optical shuffle architecture: radix, rails and planes
• Map the GB200 interconnect architecture
• Polish, pins, keys and viewing direction
• Coding, fit and qualification